Field of the Invention
The embodiments herein relate to processors and, more particularly, to a method for thread selection at various stages of a processing pipeline.
Description of the Related Art
Some processors include one or more cores that support multi-threaded instruction execution. In a multi-threaded core, at least some hardware resources within the core may be shared between two or more software threads by assigning the resources to a currently selected thread. The selected thread may change on a given core clock cycle, allowing another thread access to the core's hardware resources. As used herein, a “software thread,” “execution thread,” or simply “a thread,” refers to a smallest portion of a software application or process that may be managed independently by a core. Multi-threaded operation may allow a core to utilize processor resources more efficiently. For example, if an instruction in a first thread is waiting for a result of a memory access, processor resources may be assigned to a second thread rather than waiting for the result.
One particular hardware resource that may be shared is the instruction processing pipeline, or as referred to herein, “the processing pipeline.” The processing pipeline of a multi-threaded core may concurrently include instructions for two or more threads. Algorithms for selecting a thread to utilize the core's resources may impact performance of the core.